Please use this identifier to cite or link to this item:
Volltext verfügbar? / Dokumentlieferung
doi:10.22028/D291-47744 | Title: | Design and analysis of SIC: a provably timing-predictable pipelined processor core |
| Author(s): | Hahn, Sebastian Reineke, Jan |
| Language: | English |
| Title: | Real-Time Systems |
| Volume: | 56 |
| Issue: | 2 |
| Pages: | 207-245 |
| Publisher/Platform: | Springer Natur |
| Year of Publication: | 2019 |
| Free key words: | Timing analysis Timing predictability Timing anomalies Timing compositionality Hardware design |
| DDC notations: | 004 Computer science, internet |
| Publikation type: | Journal Article |
| DOI of the first publication: | 10.1007/s11241-019-09341-z |
| URL of the first publication: | https://doi.org/10.1007/s11241-019-09341-z |
| Link to this record: | urn:nbn:de:bsz:291--ds-477444 hdl:20.500.11880/41754 http://dx.doi.org/10.22028/D291-47744 |
| ISSN: | 1573-1383 0922-6443 |
| Date of registration: | 6-May-2026 |
| Faculty: | MI - Fakultät für Mathematik und Informatik |
| Department: | MI - Informatik |
| Professorship: | MI - Prof. Dr. Jan Reineke |
| Collections: | SciDok - Der Wissenschaftsserver der Universität des Saarlandes |
Files for this record:
There are no files associated with this item.
Items in SciDok are protected by copyright, with all rights reserved, unless otherwise indicated.