Pipeline behavior prediction for superscalar processors

Abstract

For real time systems not only the logical function is important but also the timing behavior, i. e. hard real time systems must react inside their deadlines. To guarantee this it is necessary to know upper bounds for the worst case execution times (WOETs). The accuracy of the prediction of WOETs depends strongly on the ability to model the features of the target processor. Cache memories, pipelines and parallel functional units are microarchitectural components which are responsible for the speed gain of modern processors. It is not trivial to determine their influence when predicting the worst case execution time of programs. This report describes a method to predict the behavior of piplined superscalar processors and an implementation of this approach for the SuperSPARC I microprocessor. The results of a preceding cache behavior prediction is taken into account. The method uses static program analysis. The implementation has been realized using the PAG (Program Analyzer Generator) tool. The approach is independent of the source language as it works directly on the instruction level.