Please use this identifier to cite or link to this item: doi:10.22028/D291-25841
Title: Complexity and Correctness of a Super-Pipelined Processor
Author(s): Preiß, Jochen
Language: English
Year of Publication: 2005
SWD key words: Technische Informatik
Free key words: super-pipelined processor
DDC notations: 004 Computer science, internet
Publikation type: Dissertation
Abstract: This thesis introduces the DLXπ+, a super-pipelined processor with variable cycle time. The cycle time of the DLXπ+ may be as low as 9 gate delays (including 5 gate delays for registers), which is assumed to be a lower bound for the cycle time. For the parts of the DLXπ+ that significantly differ form previous implementations correctness proofs are provided. Formulas are developed which compute restrictions to the parameters of the DLXπ+, e.g., the maximum number of reservation station entries for a given cycle time. The formulas also compute what modifications to the base design have to be made in order to realize a certain cycle time and what the impact is on the number of pipeline stages. This lays the foundation for computing the time per instruction of the DLXπ+ for a given benchmark and different cycle times in future work in order to determine the "optimum" cycle time.
Link to this record: urn:nbn:de:bsz:291-scidok-4602
Advisor: Wolfgang J. Paul
Date of oral examination: 29-Apr-2005
Date of registration: 23-Jun-2005
Faculty: MI - Fakultät für Mathematik und Informatik
Department: MI - Informatik
Collections:SciDok - Der Wissenschaftsserver der Universität des Saarlandes

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