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Titel: Achieve complete robust path delay fault testability
Verfasser: Uppaluri, Prasanti
Sparmann, Uwe
Pomeranz, Irith
Sprache: Englisch
Erscheinungsjahr: 1995
SWD-Schlagwörter: Technische Informatik
DDC-Sachgruppe: 004 Informatik
Dokumentart : Report (Bericht)
Kurzfassung: Recently, Pomeranz and Reddy [7], presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at reducing this number. Indirectly, this approach achieved complete robust path delay fault testability in very low computation times. In this paper, we use their test application scheme, however, we use morre exact measures for guiding test point insertion like test generation and RD fault identification. Thus, we reduce the number of test point needed to achieve complete testability by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable. Experimental results show that an average reduction of about 70% in the number of test points over the approach of [7] can be obtained.,
Link zu diesem Datensatz: urn:nbn:de:bsz:291-scidok-3909
hdl:20.500.11880/25885
http://dx.doi.org/10.22028/D291-25829
SciDok-Publikation: 23-Jun-2005
Fakultät: Fakultät 6 - Naturwissenschaftlich-Technische Fakultät I
Fachrichtung: MI - Informatik
Fakultät / Institution:MI - Fakultät für Mathematik und Informatik

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