Please use this identifier to cite or link to this item: doi:10.22028/D291-25829
Title: Achieve complete robust path delay fault testability
Author(s): Uppaluri, Prasanti
Sparmann, Uwe
Pomeranz, Irith
Language: English
Year of Publication: 1995
SWD key words: Technische Informatik
DDC notations: 004 Computer science, internet
Publikation type: Report
Abstract: Recently, Pomeranz and Reddy [7], presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at reducing this number. Indirectly, this approach achieved complete robust path delay fault testability in very low computation times. In this paper, we use their test application scheme, however, we use morre exact measures for guiding test point insertion like test generation and RD fault identification. Thus, we reduce the number of test point needed to achieve complete testability by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable. Experimental results show that an average reduction of about 70% in the number of test points over the approach of [7] can be obtained.,
Link to this record: urn:nbn:de:bsz:291-scidok-3909
Date of registration: 23-Jun-2005
Faculty: MI - Fakultät für Mathematik und Informatik
Department: MI - Informatik
Collections:SciDok - Der Wissenschaftsserver der Universität des Saarlandes

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